The present disclosure relates to a method of filling a via hole and an apparatus for performing the same. More specifically, the present disclosure relates to a method of filling a via hole formed in a substrate with a filling material by using an electric field and an apparatus for performing the same.
In general, semiconductor devices may be formed on a silicon wafer used as a semiconductor substrate by repeatedly performing a series of manufacturing processes, and the semiconductor devices formed as described above may be formed into semiconductor packages through a dicing process, a bonding process, and a packaging process.
Recently, 3D package technology for stacking semiconductor devices three-dimensionally has been attracting attention as the degree of integration of semiconductor devices has reached a physical limit. Particularly, a technology for commercializing a three-dimensional integrated circuit using a through silicon via (TSV) has been actively researched and developed. The TSV process technology can be classified into a via-first process for performing via hole formation and filling before the front end process, and a via-last process for performing via hole formation and filling after the front end process.
In the via-first process, via holes may be filled with polysilicon through a chemical vapor deposition process. However, since the polysilicon has a relatively high electrical resistance, device characteristics may be deteriorated. In the via-last process, via holes may be filled with copper through an electrolytic plating process. However, it is difficult to uniformly form a copper seed layer, and thus voids may be generated in the TSV electrodes. Further, it is difficult to determine the optimum condition of the electrolytic plating process.